Research Expertise:
Nanotechnology, nanoelectronics, semiconductor technology, solid-state devices, Si CMOS.
H.-S. Philip Wong
Electrical Engineering Ph.D(Lehigh University, Bethlehem, PA)
B.Sc. (Hons)   Electrical Engineering, University of Hong Kong, Hong Kong/ 1982
M.S.                  Electrical Engineering, Stony Brook University, Stony Brook, NY/ 1983
Ph.D.                Electrical Engineering, Lehigh University, Bethlehem, PA/ 1988
- 2018 – present       Vice President, Corporate Research, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, R.O.C.
- 2012 – present       Willard R. and Inez Kerr Bell Professor in the School of Engineering, Stanford Univ.
- 2004 – present       Professor of Electrical Engineering, Stanford University.
- 1988 – 2004           IBM Research, Yorktown Heights, NY.

H. Li, P. Raina, H.-S. P. Wong, “Neuro-inspired computing with emerging memories: where device physics meets learning algorithms,” invited paper, SPIE Optics+Photonics Conferences, paper 11090-129, San Diego, CA, August 11 – 15, 2019.

H.-S. P. Wong, “IC Technology – What Will the Next Node Offer Us?” invited plenary paper, Hot Chips : A Symposium on High Performance Chips, Stanford, CA, August 18 – 20, 2019.

H.-S. P. Wong , “Progress towards a carbon nanotube transistor logic technology,” invited plenary paper, NT19 : International Conference on the Science and Application of Nanotubes and Low-Dimensional Materials, Wurzburg, Germany, July 21 – 26, 2019.

X. Zheng, R. Zarcone, D. Paiton, J. Sohn, W. Wan, B. Olshausen, and H.-S. P. Wong, “Error-
Resilient Analog Image Storage and Compression with Analog-Valued RRAM Arrays: An Adaptive Joint Source-Channel Coding Approach,” International Electron Devices Meeting (IEDM), December 1 – 5, San Francisco, 2018.

T. Wu, H. Li, P.-C. Huang, A. Rahimi, J. M. Rabaey, H.-S. P. Wong, M. M. Shulaker, S. Mitra,
“Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM:
Hyperdimensional Computing Case Study,” International Solid-States Circuits Conference ( ISSCC ), paper 31.3, pp. 492 – 493, San Francisco, CA, February 11 – 15, 2018

H. Li, P. Huang, B. Gao, X. Liu, J. Kang, and H.-S. P. Wong, “Device and Circuit Interaction
Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays,” IEEE Transactions on Electron Devices, 64(12), pp.4928 – 4936, 2017.

H. Li, T. F. Wu, S. Mitra, and H.-S. P. Wong, “Resistive RAM-Centric Computing: Design and
Modeling Methodology,” IEEE Trans. Circuits and Systems I: Regular Papers, Vol. 64, No. 9, pp. 2263 – 2273 (2017).
H.-S. P. Wong and D. Akinwande, “Carbon Nanotube and Graphene Device Physics,” Cambridge University Press, 2011. ( ISBN-13: 9780521519052 )

H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F.T. Chen, M.-J. Tsai,
“Metal Oxide RRAM,” Proceedings of the IEEE, vol. 100, No. 6, pp. 1951 – 1970, June, 2012

D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, IEEE Proceedings, pp. 259-288, 2001.