Members
Research Expertise:
Physics of Semiconductor Devices, Thin Films Deposition Techniques, ULSI Technology, Deep-Submicron Devices Fabrications, Ultra-thin Oxide Preparations, Ultra-clean Processes.
Laboratory:
Tien-Sheng Chao
Professor
Ph.D. in Electronic Engineering, National Chiao Tung University

Education:

(1988-1992)  Ph. D. Institute of Electronics Engineering, NCTU, Taiwan

(1987-1988)    M. S. Institute of Electronics Engineering, NCTU, Taiwan

(1981-1985)    B. S. Dept. of Electrical and Electronics Engineering, NCTU, Taiwan


 

Research Experience:

1992/7-2001/8:     Associate Researcher / Researcher, National Nano Device Labs.

2001/8-2002/1:     Associate Prof., Dept. Of Electrophysics, NCTU

2002/2-         :     Prof., Dept. Of Electrophysics, NCTU


 

Specialization:

Physics of Semiconductor Devices, Thin Films Deposition Techniques, ULSI Technology, Deep-Submicron Devices Fabrications, Ultra-thin Oxide Preparations, Ultra-clean Processes.

 

Selected Publications:
1.

 
T. Y. Lu, T. S. Chang, S. A. Huang and T. S. Chao,” Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering,” IEEE Trans. On Electron Dev., 58(4), pp.1023-1028, Apr., 2011
 
2.

 
Y. H. Lu, P. Y. Kuo, J. W. Lin, Y. H. Wu, Y. H. Chen, and T. S. Chao, “High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels,” IEEE Electron Dev. Letts. 33 (2), pp. 215-217, FEB 2012
 
3.


 
K. T. Wang, F. C. Hsueh, Y. L. Lu, T. Y. Chiang, Y. H. Wu, C. C. Liao, L. C. Yen, T. S. Chao, “Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array,” IEEE Electron Dev. Letts., 33(6), pp.839-841, JUN 2012
 
4.

 
Y. H. Chen, L. C. Yen, T. S. Chang, T. Y. Chiang, P. Y. Kuo, T. S. Chao, “Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC,” IEEE Electron Dev. Letts., 34(8), pp.1017-1019, AUG 2013.
 
5.

 
P. Y. Kuo, Y. H. Lu, and T. S. Chao, “High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETs,” IEEE Trans.  on Electron Device, 61(11), pp. 3821-3826, 2014